Stargrazer One: A New Architecture for Distributed Maximum Power Point Tracking of Solar Photovoltaic Sources

The yield from a solar photovoltaic (PV) source is dependent on factors such as light and temperature. A control system called a maximum power point tracker (MPPT) ensures that the yield from a solar PV source is maximized in spite of these factors. This thesis presents a novel implementation of a perturb and observe (PO) MPPT. The implementation uses a switched capacitor step down converter and a custom digital circuit implementation of the PO algorithm. Working in tandem, the switched capacitor step down converter and the custom digital circuit implementation were able to successfully track the maximum power point of a simulated solar PV source. This implementation is free of the overhead encountered with general purpose processor based MPPT implementations. This makes this MPPT system a valid candidate for applications where general purpose processors are undesirable. This document will begin by discussing the current state of MPPT research. Afterward, this thesis will present studies done to be able to use the chosen switched capacitor step down converter. Then the digital circuit PO implementation will be discussed in detail. Simulations of the architecture will be presented. Finally, experimental validation using a hardware prototype will be shown

RESOURCE EFFICIENT DESIGN OF QUANTUM CIRCUITS FOR CRYPTANALYSIS AND SCIENTIFIC COMPUTING APPLICATIONS

Quantum computers offer the potential to extend our abilities to tackle computational problems in fields such as number theory, encryption, search and scientific computation. Up to a superpolynomial speedup has been reported for quantum algorithms in these areas. Motivated by the promise of faster computations, the development of quantum machines has caught the attention of both academics and industry researchers. Quantum machines are now at sizes where implementations of quantum algorithms or their components are now becoming possible. In order to implement quantum algorithms on quantum machines, resource efficient circuits and functional blocks must be designed. In this work, we propose quantum circuits for Galois and integer arithmetic. These quantum circuits are necessary building blocks to realize quantum algorithms. The design of resource efficient quantum circuits requires the designer takes into account the gate cost, quantum bit (qubit) cost, depth and garbage outputs of a quantum circuit. Existing quantum machines do not have many qubits meaning that circuits with high qubit cost cannot be implemented. In addition, quantum circuits are more prone to errors and garbage output removal adds to overall cost. As more gates are used, a quantum circuit sees an increased rate of failure. Failures and error rates can be countered by using quantum error correcting codes and fault tolerant implementations of universal gate sets (such as Clifford+T gates). However, Clifford+T gates are costly to implement with the T gate being significantly more costly than the Clifford gates. As a result, designers working with Clifford+T gates seek to minimize the number of T gates (T-count) and the depth of T gates (T-depth). In this work, we propose quantum circuits for Galois and integer arithmetic with lower T-count, T-depth and qubit cost than existing work. This work presents novel quantum circuits for squaring and exponentiation over binary extension fields (Galois fields of form GF(2 m )). The proposed circuits are shown to have lower depth, qubit and gate cost to existing work. We also present quantum circuits for the core operations of multiplication and division which enjoy lower T-count, T-depth and qubit costs compared to existing work. This work also illustrates the design of a T-count and qubit cost efficient design for the square root. This work concludes with an illustration of how the arithmetic circuits can be combined into a functional block to implement quantum image processing algorithms